1. Field of the Invention
The present invention relates to a DRAM having a stacked type capacitor and, more specifically, to an improvement of a structure of a capacitor which increases signal charge storing capacity.
2. Description of the Background Art
A dynamic random access memory (DRAM) is a semiconductor memory device capable of random input/output of memory information. Generally, the DRAM comprises a memory cell array which is a memory region for storing information and peripheral circuits necessary for the exchange of information with the outside. FIG. 6 is a block diagram showing a general structure of a DRAM. Referring to the figure, the DRAM 50 comprises a memory cell array 51 for storing signals for transmitting memory information; a row & column address buffer 52 for receiving external address signals to select a memory cell constituting a unit storage circuit; a row decoder 53 and a column decoder 54 for designating the memory cell by decoding the address signals; a sense refresh amplifier 55 for amplifying and reading the signal stored in the designated memory cell; a data in buffer 56 and a data out buffer 57 for inputting/outputting data; and a clock generator 58 for generating clock signals.
FIG. 7 is an equivalent circuit diagram of a memory cell including a pair of bit lines in the memory cell array 51. Referring to FIG. 7, the memory cell comprises one transfer gate transistor 2 and one capacitor 10. The transfer gate transistor 2 has its gate connected to a word line 4, one of the source.multidot.drain regions connected to a bit line 26 and the other one of the source.multidot.drain regions connected to a capacitor 10.
Writing of data to the memory cell is carried out in the following manner. At first the word line 4 is activated and the transfer gate transistor 2 is turned on. Potential of high level or low level corresponding to the information to be written is applied to the bit line 26. Charges corresponding to the potential of the bit line 26 are stored in the capacitor 10. Then the word line 4 is inactivated, and transfer gate transistor 2 is turned off. Consequently, charges corresponding to the data are stored in the capacitor 10.
The reading operation is carried out in the following manner. The bit line 26 is held in an electrically isolated floating state in advance. When the word line 4 is activated, the transfer gate transistor 2 is turned on. The charges stored in the capacitor 10 are applied to the bit line 26. Consequently, potential change as small as several 100 mV appears on the bit line 26. The appeared potential change is amplified by the sense amplifier 55 to be the read signal.
In this manner, in reading, the charges representing information stored in the capacitor 10 are distributed again to the bit line 26, and the potential change at that time is detected. The capacity of the capacitor 10 is in proportion to the increase/decrease of the surface area of the electrode thereof. Consequently, if the capacitor size is reduced to increase degree of integration, the amount of signal charges stored is reduced. Accordingly, the potential change to be detected is also reduced, resulting in possible misreading. In addition, as the amount of signal charges is reduced, the memory cells become less immune to the soft errors. In view of the foregoing, improvement of capacitor structure has been done in order to ensure the amount of charges stored in the capacitor, that is, the capacity, even if the planar size of the capacitor is reduced as the degree of integration is increased.
One such example will be described. FIGS. 8A and 8B are a partial plan view of a memory cell array in the DRAM and a cross sectional view taken a long the line VIII--VIII, respectively. The DRAM shown in this example is disclosed in, for example, "NOVEL STACKED CAPACITOR CELL FOR 64 Mb DRAM" ('89 Symposium on VLSI Technology Digest of Technical Papers, pp69-70, W. Wakamiya et al.).
FIGS. 8A and 8B show memory cells of 6 bits and 3 bits, respectively. Referring to FIGS. 8A and 8B, a field shield gate electrode 20 is formed in an element separating region of a surface of a p type silicon substrate 1, with a gate insulating film 21 formed therebetween. A plurality of memory cells are formed in an element forming region on the surface of the p type silicon substrate 1 surrounded by the field shield gate electrode 20. The memory cell comprises one transfer gate transistor 2 and one capacitor 10.
The transfer gate transistor 2 comprises a pair of n.sup.30 impurity regions (source.multidot.drain) 5,5 formed on the surface of the p type silicon substrate 1, and a gate electrode (word line) 4 formed on the surface region of the p type silicon substrate 1 sandwiched by the pair of n.sup.+ impurity regions 5,5, with a gate oxide film 3 formed therebetween. The periphery of the gate electrode 4 is covered by an insulating film 6.
The capacitor 10 comprises a lower electrode (storage node) 11, a dielectric layer 12 formed covering the surface of the lower electrode 11, and an upper electrode (cell plate) 13 formed thereon. The lower electrode 11 comprises a first portion 11a connected to one of the n.sup.30 impurity regions 5 of the transfer gate transistor 2, and a cylindrical second portion 11b extending operate from the main surface of the substrate. The dielectric layer 12 is especially formed along the inner and outer surfaces of the second portion 11b of the lower electrode 11. Therefore, this portion contributes to increase the capacitor capacity. The capacitor having such structure is called a cylindrical capacitor.
A bit line 26 is connected through a contact hole 25 formed in the interlayer insulating layer 27 is connected to the other one of the n.sup.+ impurity regions 5 of the transfer gate transistor 2, which is not connected to the capacitor 10. Word lines 4,4 are formed on the upper portion of the field shield gate electrode 20, with an insulating film 22 formed therebetween. A portion of the capacitor 10 extends to the upper portion of the word line 4 through the insulating film 6 and the nitride film 14.
As described the above, in a conventional DRAM, a cylindrical portion is formed in the capacitor to increase the capacity thereof. However, the height of the cylindrical capacitor is limited by the interconnection structure and by conditions for manufacturing. Further, as the degree of the integration is further improved, the planar area of occupation of the capacitor 10 becomes smaller, and accordingly, the diameter of the cylindrical portion of the capacitor 10 must be made smaller. A novel structure of a capacitor which can ensure prescribed capacitor capacity in higher degree of integration has been desired.